UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 240

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Various cautions concerning the 16-bit timer/event counter are shown below.
(1) If a conflict occurs between the reading of the CCn0 register and a capture operation when the CCn0 register
(2) If a conflict occurs between the reading of the CCn1 register and a capture operation when the CCn1 register
(3) The following bits and registers must not be rewritten during operation (TMCEn = 1).
(4) The TMCAEn bit of the TMCn0 register is a TMn reset signal. To use TMn, first set (1) the TMCAEn bit.
(5) The analog noise elimination time + two cycles of the input clock are required to detect the valid edge of the
(6) The operation of an external interrupt request signal (INTCCn0 or INTCCn1) is automatically determined
(7) If the ENTOn and ALVn bits are changed at the same time, a glitch (spike shaped noise) may be generated in
Cautions
is used in capture mode, an external trigger (INTPn0) valid edge is detected and an external interrupt request
signal (INTCCn0) is generated, however, the timer value is not stored in the CCn0 register.
is used in capture mode, an external trigger (INTPn1) valid edge is detected and an external interrupt request
signal (INTCCn1) is generated, however, the timer value is not stored in the CCn1 register.
• CSn2 to CSn0 bits of TMCn0 register
• TMCn1 register
• SESn register
external interrupt request signal (INTPn0 or INTPn1) or the external clock input (TIn). Therefore, edge
detection will not be performed normally for changes that are less than the analog noise elimination time + two
cycles of the input clock. Only two clocks of f
valid edge.
according to the operating state of the capture/compare register. When the capture/compare register is used
for a capture operation, the external interrupt request signal is used for valid edge detection. When the
capture/compare register is used for a compare operation, the external interrupt request signal is used for an
interrupt indicating a match with the TMn register.
the TOn pin output. Either create a circuit configuration that will not malfunction even if a glitch is generated or
make sure that the ENTOn and ALVn bits are not changed at the same time.
Remark
n = 0, 1
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
User’s Manual U15905EJ2V1UD
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are required for detection of the internal clear input (TCLR1n)