UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 301
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 301 of 555
- Download datasheet (4Mb)
13.1 Features
• Transfer rate: 300 bps to 312.5 kbps (using a dedicated baud rate generator and an internal system clock of 20
• Full-duplex communications
• Two-pin configuration
• Reception error detection functions
• Interrupt sources: 3 types
• The character length of transmit/receive data is specified by the ASIMn register
• Character length: 7 or 8 bits
• Parity functions: Odd, even, 0, or none
• Transmission stop bits: 1 or 2 bits
• On-chip dedicated baud rate generator
Remark
MHz)
On-chip receive buffer register n (RXBn)
On-chip transmit buffer register n (TXBn)
TXDn: Transmit data output pin
RXDn: Receive data input pin
• Parity error
• Framing error
• Overrun error
• Reception error interrupt (INTSREn):
• Reception completion interrupt (INTSRn):
• Transmission completion interrupt (INTSTn): Interrupt is generated when the serial transmission of transmit
n = 0, 1
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
User’s Manual U15905EJ2V1UD
Interrupt is generated according to the logical OR of the three
types of reception errors
Interrupt is generated when receive data is transferred from the
shift register to receive buffer register n after serial transfer is
completed during a reception enabled state
data (8 or 7 bits) from the shift register is completed
299
Related parts for UPD70F3201YGC-YEU-A
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT STARTER FOR M16C/29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/2D
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
R0K33062P STARTER KIT
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/23 E8A
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/25
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER H8S2456 SHARPE DSPLY
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C38C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C35C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8CL3AC+LCD APPS
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR RX610
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R32C/118
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV RSK-R8C/26-29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR SH7124
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR H8SX/1622
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV FOR SH7203
Manufacturer:
Renesas Electronics America
Datasheet: