UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 480

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.2.2 Correction control register (CORCN)
20.3 ROM Correction Operation and Program Flow
478
This register disables or enables the correction operation of correction address register n (CORADn) (n = 0 to 3).
Each channel can be enabled or disabled by this register.
This register can be read or written in 8-bit or 1-bit units.
This register is cleared to 00H after reset.
<1> If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by
<2> When the DBTRAP instruction is executed, execution branches to address 00000060H.
<3> Software processing after branching causes the result of ROM correction to be judged (the fetch address and
<4> After the correction software has been executed, the return address is set, and return processing is started
Cautions 1. The software that performs <3> and <4> must be executed in the internal ROM/RAM.
Remark
the DBTRAP instruction.
ROM correction operation are confirmed) and execution to branch to the correction software.
by the DBRET instruction.
2. Develop the program so that the ROM correction function is not used until data has been
3. When setting an address to be corrected to the CORADn register, clear the higher bits to 0 in
4. The ROM correction function cannot be used to correct the data of the internal ROM. It can
n = 0 to 3
Table 20-1. Correspondence Between CORCN Register Bits and CORADn Registers
CORCN
completely written to the CORCN register that controls ROM correction.
accordance with the capacity of the internal ROM. Before setting, make sure that the CORCN
register is 00H.
only be used to correct instruction codes. If ROM correction is used to correct data, that data
is replaced with the DBTRAP instruction code.
After reset:
COREN3
COREN2
COREN1
COREN0
CORENn
00H
0
1
0
CORCN Register Bit
Disabled
Enabled
CHAPTER 20 ROM CORRECTION FUNCTION
R/W
0
Address:
User’s Manual U15905EJ2V1UD
0
Enables/disables correction operation
FFFFF880H
0
CORAD3
CORAD2
CORAD1
CORAD0
Corresponding CORADn Register
COREN3 COREN2 COREN1 COREN0
3
2
1
0