UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 195

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.8
5.8.1
external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the
bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again.
peripheral I/O register or the external memory is accessed.
configuration multi-processor type systems in which two or more bus masters exist.
function or a bit manipulation instruction.
CPU bus lock
Read-modify-write access of bit
manipulation instruction
The HLDAK and HLDRQ functions are valid if the PCM2 and PCM3 pins are set in the control mode.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until a
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing
Bus Hold Function
Functional outline
Status
Data Bus
16 bits
8 bits
Width
−
CHAPTER 5 BUS CONTROL FUNCTION
User’s Manual U15905EJ2V1UD
Word access to even address
Word access to odd address
Halfword access to odd address
Word access
Halfword access
Access Type
−
Between first and second access
Between first and second access
Between second and third access
Between first and second access
Between first and second access
Between second and third access
Between third and fourth access
Between first and second access
Between read access and write
access
Timing in Which Bus Hold Request
Not Acknowledged
193