UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 475
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.3 Operation
(WDTRES).
consumption of the system can be reduced.
register: 2
system clock oscillator does not stop.
The system is reset, initializing each hardware unit, when a low level is input to the RESET pin by WDT overflow
While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power
If the RESET pin goes high or if WDTRES is received, the reset status is released.
If the reset status is released by RESET pin input, the oscillation stabilization time elapses (reset value of OSTS
If the reset status is released by WDTRES, the oscillation stabilization time is not inserted because the main
Note Reset by WDT overflow (WDTRES) is valid only when the WDTM4 and WDTM3 bits of the watchdog timer
19
mode register (WDTM) are set to “11” (refer to 10.3 (3)).
/f
X
) and then the CPU starts program execution.
CHAPTER 19 RESET FUNCTION
User’s Manual U15905EJ2V1UD
473
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