UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 328

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

326
(c) Baud rate
(d) Baud rate error
Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable
The baud rate is the value obtained by the following formula.
f
k = Value set by MDLn7 to MDLn0 bits of BRGCn register (k = 8, 9, 10, ..., 255)
The baud rate error is obtained by the following formula.
CKSR
Example
= Frequency [Hz] of base clock (Clock) selected by TPSn3 to TPSn0 bits of CKSRn register.
2. Make sure that the baud rate error during reception is within the allowable baud rate
error of the reception destination.
range described in (4) Allowable baud rate range during reception.
Error
Base clock frequency = 20 MHz = 20,000,000 Hz
Setting of MDLn7 to MDLn0 bits in BRGC0 register = 01000001B (k = 65)
Target baud rate = 153,600 bps
Baud rate = 20M/(2 × 65)
Error = (153,846/153,600 − 1) × 100
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
(%)
= 0.160 [%]
=

 

= 20,000,000/(2 × 65) = 153,846 [bps]
Actual
Desired
baud
User’s Manual U15905EJ2V1UD
baud
Baud rate =
rate
rate
(baud
(normal
f
2 × k
CKSR
rate
baud
[bps]
with
rate)
error)
−
1

 

×
100
[%]