UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 366

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4 I
364
(1) Pin configuration
2
The serial clock pin (SCL) and serial data bus pin (SDA) are configured as follows.
SCL ..............This pin is used for serial clock I/O.
SDA .............This pin is used for serial data I/O.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external
pull-up resistor is required.
C Bus Mode Functions
Clock output
(Clock input)
Data output
Data input
Master device
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Figure 15-5. Pin Configuration Diagram
SCL
SDA
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
V
V
DD
DD
2
C BUS
SDA
SCL
Slave device
(Clock output)
Clock input
Data output
Data input