UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 398
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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is set to 1, a communication reservation can be made by setting bit 1 (STT) of the IIC control register (IICC) to 1
before a stop condition is detected.
396
SDA
SCL
The communication reservation timing is shown below.
Communication reservations are accepted of the following timing. After bit 1 (STD) of the IIC status register (IICS)
Hardware processing
1
Program processing
IIC:
STT:
STD: Bit 1 of IIC status register (IICS)
SPD: Bit 0 of IIC status register (IICS)
SDA
SPD
STD
SCL
2
IIC shift register
Bit 1 of IIC control register (IICC)
3
Figure 15-15. Timing for Accepting Communication Reservations
4
Communication
reservation
STT
= 1
Figure 15-14. Communication Reservation Timing
5
6
7
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Standby mode
8
9
Output by master with bus access
2
C BUS
Set SPD
and INTIIC
Write to
IIC
Set
STD
1
2
3
4
5
6
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