UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 435

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3 Maskable Interrupts
have 38 to 40 maskable interrupt sources.
the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt
control registers (programmable priority control).
disabled and the interrupt disabled (DI) status is set.
enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt
control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same
priority level cannot be nested.
instruction, and execute the DI instruction before the RETI instruction to restore the original values of EIPC and
EIPSW.
interrupt functions as a maskable interrupt (INTWDTM).
17.3.1 Operation
handler routine.
interrupt is being serviced (while PSW.NP = 1 or PSW.ID = 1) are held pending inside INTC. In this case, servicing a
new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request if either the
maskable interrupt is unmasked or PSW.NP and PSW.ID are cleared to 0 by using the RETI or LDSR instruction.
Maskable interrupt requests can be masked by interrupt control registers. The V850ES/SA2 and V850ES/SA3
If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to
When an interrupt request has been acknowledged, the acknowledgment of other maskable interrupt requests is
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
To enable multiple interrupts, however, save EIPC and EIPSW to memory or registers before executing the EI
If the WDTM4 bit of the watchdog timer mode register (WDTM) is cleared to 0, the watchdog timer overflow
If a maskable interrupt occurs by INT input, the CPU performs the following processing, and transfers control to a
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the ID bit of the PSW and clears the EP bit.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request masked by INTC and the maskable interrupt request generated while another
How maskable interrupts are serviced is illustrated below.
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U15905EJ2V1UD
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