UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 457

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.7 Interrupt Acknowledge Time of CPU
requests successively, input the next interrupt at least 4 clocks after the preceding interrupt.
Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt
• In software/hardware STOP mode
• When the external bus is accessed
• When interrupt request non-sampling instructions are successively executed (Refer to 17.8 Periods in Which
• When the interrupt control register is accessed
• When a peripheral I/O register is accessed
Remark
Interrupts Are Not Acknowledged by CPU.)
Minimum
Maximum
Interrupt acknowledge time (internal system clock)
INT1 to INT4: Interrupt acknowledgment processing
IFX:
IDX:
Figure 17-14. Pipeline Operation at Interrupt Request Acknowledgment (Outline)
Interrupt acknowledgment operation
Internal interrupt
Instruction (start instruction of
4
6
interrupt service routine)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Invalid instruction fetch
Invalid instruction decode
Interrupt request
Internal clock
Analog delay time
Analog delay time
External interrupt
Instruction 1
Instruction 2
4 +
6 +
User’s Manual U15905EJ2V1UD
The following cases are exceptions.
• In IDLE/software STOP mode
• External bus access
• Two or more interrupt request non-sample instructions are
• Access to peripheral I/O register
IF
executed in succession
Access to interrupt control register
INT1 INT2 INT3 INT4
IFX IDX
ID
4 system clocks
EX
DF
WB
Condition
IF
IF
ID
EX
455