UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 326

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

324
(2) Serial clock generation
Caution Set the UARTCAEn bit of the ASIMn register to 0 before rewriting the TPSn3 to TPSn0 bits.
Remark
A serial clock can be generated according to the settings of the CKSRn and BRGCn registers.
The base clock to the 8-bit counter is selected by the TPSn3 to TPSn0 bits of the CKSRn register.
The 8-bit counter divisor value can be set by the MDLn7 to MDLn0 bits of the BRGCn register.
(a) Clock select register n (CKSRn)
The CKSRn register is an 8-bit register for selecting the basic block using the TPSn3 to TPSn0 bits. The
clock selected by the TPSn3 to TPSn0 bits becomes the base clock (Clock) of the transmission/reception
module. Its frequency is referred to as f
This register can be read or written in 8-bit units.
This register is cleared to 00H after reset.
n = 0, 1
m = 4, 5 (m = 4 when n = 0, m = 5 when n = 1)
CKSRn
After reset:
Other than above
TPSn3
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
00H
0
0
0
0
0
0
0
0
1
1
1
1
7
0
TPSn2
R/W
0
0
0
0
1
1
1
1
0
0
0
0
6
0
Address: CKSR0
TPSn1
User’s Manual U15905EJ2V1UD
0
0
1
1
0
0
1
1
0
0
1
1
5
0
CKSR
TPSn0
.
0
1
0
1
0
1
0
1
0
1
0
1
4
0
FFFFFA06H, CKSR1 FFFFFA16H
f
f
f
f
f
f
f
f
f
f
f
TOm output
Setting prohibited
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
TPSn3
/2
/4
/8
/16
/32
/64
/128
/256
/512
/1,024
3
Receive operation
TPSn2
2
TPSn1
1
TPSn0
0