UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 419

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.4 DMA Bus States
16.4.1 Types of bus states
The DMAC bus states consist of the following 10 states.
(1) TI state
(2) T0 state
(3) T1R state
(4) T1RI state
(5) T2R state
(6) T2RI state
(7) T1W state
(8) T1WI state
(9) T2W state
(10) TE state
The TI state is an idle state, during which no access request is issued.
The DMA request signals are sampled at the rising edge of the CLKOUT signal.
DMA transfer ready state (state in which a DMA transfer request has been issued and the bus mastership is
acquired for the first DMA transfer).
The bus enters the T1R state at the beginning of a read operation in the two-cycle transfer mode.
Address driving starts. After entering the T1R state, the bus invariably enters the T2R state.
The T1RI state is a state in which the bus waits for the acknowledge signal corresponding to an external
memory read request.
After entering the last T1RI state, the bus invariably enters the T2R state.
The T2R state corresponds to the last state of a read operation in the two-cycle transfer mode, or to a wait
state.
In the last T2R state, read data is sampled. After entering the last T2R state, the bus invariably enters the
T1W state.
State in which the bus is ready for DMA transfer to on-chip peripheral I/O or internal RAM (state in which the
bus mastership is acquired for DMA transfer to on-chip peripheral I/O or internal RAM).
After entering the last T2RI state, the bus invariably enters the T1W state.
The bus enters the T1W state at the beginning of a write operation in the two-cycle transfer mode.
Address driving starts. After entering the T1W state, the bus invariably enters the T2W state.
State in which the bus waits for the acknowledge signal corresponding to an external memory write request.
After entering the last T1WI state, the bus invariably enters the T2W state.
The T2W state corresponds to the last state of a write operation in the two-cycle transfer mode, or to a wait
state.
In the last T2W state, the write strobe signal is made inactive.
The TE state corresponds to DMA transfer completion. The DMAC generates the internal DMA transfer
completion signal and various internal signals are initialized (n = 0 to 3). After entering the TE state, the bus
invariably enters the TI state.
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U15905EJ2V1UD
417