UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 243

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) 8-bit timer counters 2 to 5 (TM2 to TM5)
(2) 8-bit timer compare registers 2 to 5 (CR2 to CR5)
The TMn register is an 8-bit read-only register that counts the count pulses.
The counter is incremented in synchronization with the rising edge of the count clock.
TM2 and TM3, and TM4 and TM5 can be used as 16-bit timers when they are connected in cascade. When
these timers are used as 16-bit timers, their values can be read by using a 16-bit memory manipulation
instruction. However, because these registers are connected by an internal 8-bit bus, the TMm register and
TMm+1 register must be read divided into two times. Therefore, read these registers twice and compare the
values, taking into consideration that the reading occurs during a count change.
In the following cases, the count value becomes 00H.
• After reset
• When the TMCEn bit of 8-bit timer mode control register n (TMCn) is cleared
• TMn register and CRn register match in the mode in which clear & start occurs on a match between the TMn
Caution When connected in cascade, these registers become 00H even when the TCEm bit in the
Remark
The CRn register can be read and written in 8-bit units.
In a mode other than the PWM mode, the value set to the CRn register is always compared to the count value
of 8-bit counter n (TMn), and if the two values match, an interrupt request signal (INTTMn) is generated.
In the PWM mode, TMn register overflow causes the TOn pin output to change to the active level, and when
the values of the TMn register and the CRn register match, the TOn pin output changes to the inactive level.
The value of the CRn register can be set in the range of 00H to FFH.
When TM2 and TM3, and TM4 and TM5 are connected in cascade as 16-bit timers, the CRm register and
CRm+1 register function as 16-bit timer compare registers 23 and 45 (CR23 and CR45). The counter value
and register value are compared in 16-bit lengths, and if they match, an interrupt request (INTTMm) is
generated.
Cautions 1. In the mode in which clear & start occurs upon a match of the TMn register and CRn
Remark
register and 8-bit timer compare register n (CRn)
2. In the PWM mode, set the CRn register rewrite interval to three or more count clocks
3. Before changing the value of the CRn register when using a cascade connection, be sure
lowest timer (TMm) is cleared.
n = 2 to 5
m = 2, 4
n = 2 to 5
m = 2, 4
register (TMCn6 =0), do not write a different value to the CRn register during the count
operation.
(clock selected with timer clock selection register n (TCLn)).
to stop the timer operation.
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
User’s Manual U15905EJ2V1UD
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