UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 183

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.5
5.5.1
5.5.2
register.
Bus Cycle Type
Instruction fetch (normal access)
Instruction fetch (branch)
Operand data access
The following table shows the number of basic clocks required for accessing each resource.
Note 2 + n clocks (n: Number of wait states) when the separate bus mode is selected.
Remark
The bus size of each external memory area selected by CSn can be set (to 8 bits or 16 bits) by using the BSC
The external memory area of the V850ES/SA2 (0100000H to 0BFFFFFH) is selected by CS0 to CS3.
The external memory area of the V850ES/SA3 (0100000H to 0FFFFFFH) is selected by CS0 to CS3.
(1) Bus size configuration register (BSC)
Caution Be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0.
Bus Access
This register can be read or written in 16-bit units.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not
Number of clocks for access
Bus size setting function
Unit: Clocks/access
After reset:
access an external memory area other than the one for this initialization routine until the
initial settings of the BSC register are complete. However, external memory areas whose
initial settings are complete may be accessed.
BSC
CSn signal
Area (Bus Width)
BSn0
15
5555H
0
7
0
0
1
8 bits
16 bits
BS30
CS3
14
1
6
R/W
CHAPTER 5 BUS CONTROL FUNCTION
Internal ROM (32 Bits)
Data bus width of CSn space (n = 0 to 3)
User’s Manual U15905EJ2V1UD
Address:
13
0
5
0
1
2
3
BS20
FFFFF066H
CS2
12
1
4
11
0
0
3
Internal RAM (32 Bits)
BS10
CS1
10
1
2
1 or 2
1 or 2
1
0
1
0
9
BS00
External Memory (16 Bits)
CS0
1
8
0
3 + n
3 + n
3 + n
Note
Note
Note
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