UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 224

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UPD70F3201YGC-YEU-A

Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet

Specifications of UPD70F3201YGC-YEU-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.5
222
(1) Count operation
Remark
Operation
The 16-bit timer/event counter can function as a 16-bit free-running timer or as an external signal event
counter. The setting for the type of operation is specified by timer mode control registers n0 and n1 (TMCn0
and TMCn1) (n = 0, 1).
When it operates as a free-running timer, if the CCn0 or CCn1 register and the TMn register count value
match, an interrupt signal is generated and the timer output signal (TOn) can be set or reset. Also, a capture
operation that holds the TMn register count value in the CCn0 or CCn1 register is performed, in
synchronization with the valid edge that was detected from the external interrupt request input pin as an
external trigger. The capture value is held until the next capture trigger is generated.
Caution When using the INTPn0/TIn0 pin as an external clock input pin (TIn0), be sure to disable the
Count clock
n = 0, 1
TMn
INTPn0 interrupt and set CCn0 to compare mode (n = 0, 1).
Count start
TMCEn←1
0000H
Figure 7-2. Basic Operation of 16-Bit Timer/Event Counter
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
0001H
0002H 0003H
User’s Manual U15905EJ2V1UD
FBFEH FBFFH
Count disabled
TMCEn←0
0000H
Count start
TMCEn←1
0001H 0002H

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