UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 444

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2)
registers is equivalent to the xxMKn bit of the xxICn register.
these registers can be read or written in 8-bit or 1-bit units (m = 0 to 2).
to 1. If these bits are not 1, the operation cannot be guaranteed.
442
These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR2
The IMRm register can be read or written in 16-bit units (m = 0 to 2).
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,
Bits 15 to 6 of the IMR2 register (bits 7 to 0 of the IMR2H register and bits 7 and 6 of the IMR2L register) are fixed
These registers are set to FFFFH after reset.
Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. If a bit is
Note This bit is valid only for the V850ES/SA3. In the V850EA/SA2, be sure to set this bit to 1.
Remark
manipulated using the name of xxMKn, the contents of the xxICn register, instead of the IMRm
register, are rewritten (as a result, the contents of the IMRm register are also rewritten).
xx: Identification name of each peripheral unit (AD, BRG, CC, CSI, DMA, IIC, OVF, D, ROV, RTC,
n:
After reset:
After reset:
After reset:
IMR2
IMR1
IMR0
SRE, ST, TM, WDT).
Peripheral unit number (None, or 0 to 3)
SRMK0
TMMK2
xxMKn
ADMK
PMK6
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
15
15
15
FFFFH
1
1
FFFFH
FFFFH
0
1
7
7
7
CSIMK4
SREMK0
OVFMK1
Interrupt servicing enabled
Interrupt servicing disabled
PMK5
14
14
14
1
6
1
6
6
R/W
R/W
R/W
Note
CCMK11
BRGMK
CSIMK3
CSIMK1
PMK4
User’s Manual U15905EJ2V1UD
13
13
13
Address:
1
Address:
Address:
5
5
5
Interrupt mask flag setting
CCMK10
OVFMK
STMK1
IICMK
PMK3
FFFFF104H
FFFFF102H
FFFFF100H
12
12
12
1
4
4
4
DMAMK3
OVFMK0
CSIMK0
SRMK1
PMK2
11
11
11
1
3
3
3
DMAMK2
SREMK1
CCMK01
TMMK5
PMK1
10
10
10
1
2
2
2
DMAMK1
CCMK00
CSIMK2
TMMK4
PMK0
9
1
1
9
1
9
1
DMAMK0
WDTMK
TMMK3
RTCMK
STMK0
1
8
0
8
0
8
0