UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 225
UPD70F3201YGC-YEU-A
Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet
1.UPD70F3201YGC-YEU-A.pdf
(555 pages)
Specifications of UPD70F3201YGC-YEU-A
Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(2) Overflow
Remark
TMn
INTOVFn
When the TMn register has counted the count clock from FFFFH to 0000H, the OVFn bit of the TMCn0 register
is set (1), and an overflow interrupt (INTOVFn) is generated at the same time (n = 0, 1). However, if the CCn0
register is set to compare mode (CMSn0 bit = 1) and to the value FFFFH when match clearing is enabled
(CCLRn bit = 1), then the TMn register is considered to be cleared and the OVFn bit is not set (1) when the
TMn register changes from FFFFH to 0000H. Also, the overflow interrupt (INTOVFn) is not generated .
When the TMn register is changed from FFFFH to 0000H because the TMCEn bit changes from 1 to 0, the
TMn register is considered to be cleared, but the OVFn bit is not set (1) and no INTOVFn interrupt is
generated.
Also, timer operation can be stopped after an overflow by setting the OSTn bit of the TMCn1 register to 1.
When the timer is stopped due to an overflow, the count operation is not restarted until the TMCEn bit of the
TMCn0 register is set (1).
Operation is not affected even if the TMCEn bit is set (1) during a count operation.
Remark
0
n = 0, 1
n = 0, 1
OSTn ← 1
Figure 7-3. Operation After Overflow (When OSTn = 1)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
TMCEn ← 1
Count
start
User’s Manual U15905EJ2V1UD
Overflow
FFFFH
TMCEn ← 1
Overflow
FFFFH
223
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