UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 464

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.3 IDLE Mode
18.3.1 Setting and operation status
of the power save control register (PSC) to 1 in the normal operation mode.
functions stops.
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with the subclock or an external clock continue operating.
the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be
restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same
manner as when the HALT mode is released.
18.3.2 Releasing IDLE mode
request (INTP0 to INTP6 pin input), unmasked internal interrupt request from the peripheral functions operable in the
IDLE mode, or RESET input.
462
Non-maskable interrupt request
Maskable interrupt request
The IDLE mode is set by clearing the PSM bit of the power save mode register (PSMR) to 0 and setting the STP bit
In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral
As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are
Table 18-5 shows the operation status in the IDLE mode.
The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of
Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to
The IDLE mode is released by a non-maskable interrupt request (NMI pin input), unmasked external interrupt
After the IDLE mode has been released, the normal operation mode is restored.
(1) Releasing IDLE mode by non-maskable interrupt request or unmasked maskable interrupt request
The IDLE mode is released by a non-maskable interrupt request or an unmasked maskable interrupt request,
regardless of the priority of the interrupt request. If the IDLE mode is set in an interrupt servicing routine,
however, an interrupt request that is issued later is processed as follows.
(a) If an interrupt request with a priority lower than that of the interrupt request currently being serviced is
(b) If an interrupt request with a priority higher than that of the interrupt request currently being serviced is
issued, only the IDLE mode is released, and that interrupt request is not acknowledged. The interrupt
request itself is retained.
issued (including a non-maskable interrupt request), the IDLE mode is released and that interrupt request
is acknowledged.
Release Source
set the IDLE mode.
Table 18-4. Operation After Releasing IDLE Mode by Interrupt Request
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
CHAPTER 18 STANDBY FUNCTION
Interrupt Enabled (EI) Status
User’s Manual U15905EJ2V1UD
The next instruction is executed
Interrupt Disabled (DI) Status