UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 529

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

I
(T
2
C bus mode (
SCL clock frequency
Bus-free time (between stop/start
conditions)
Hold time
SCL clock low-level width
SCL clock high-level width
Setup time for start/restart
conditions
Data hold time
Data setup time
SDA and SCL signal rise time
SDA and SCL signal fall time
Stop condition setup time
Pulse width with spike
suppressed by input filter
Capacitance load of each bus line
A
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
Remark
= −40 to +85°C, V
2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at V
3. If the system does not extend the SCL signal low hold time (t
4. The high-speed-mode I
5. Cb: Total capacitance of one bus line (unit: pF)
Note 1
Parameter
signal) in order to occupy the undefined area at the falling edge of SCL.
(t
speed-mode I
• If the system does not extend the SCL signal’s low state hold time:
• If the system extends the SCL signal’s low state hold time:
The maximum operating frequency of the
is f
HD:DAT
µ
t
Transmit the next data bit to the SDA line prior to releasing the SCL line (t
= 1,250 ns: Normal mode I
SU
XX
PD703200Y, 703201Y, 703204Y, 70F3201Y, 70F3204Y only)
CBUS
compatible
master
I
:
2
DAT
= 17 MHz.
C mode
) needs to be satisfied.
DD
≥ 250 ns
= AV
2
C bus so that it meets the following conditions.
DD
= EV
f
t
t
t
t
t
t
t
t
t
t
t
Cb
CLK
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
CHAPTER 22 ELECTRICAL SPECIFICATIONS
2
DD
C bus can be used in a normal-mode I
Symbol
= 2.2 to 2.7 V, V
2
C bus specification).
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User’s Manual U15905EJ2V1UD
MIN.
0
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
Note 2
µ
SS
0
−
−
−
−
Normal Mode
PD703200Y, 703201Y, 703204Y, 70F3201Y, and 70F3204Y
= AV
SS
= EV
MAX.
1,000
100
300
400
−
−
−
−
−
−
−
−
−
−
SS
= 0 V)
2
C bus system. In this case, set the high-
LOW
20 + 0.1Cb
20 + 0.1Cb
), only the maximum data hold time
100
MIN.
0
1.3
0.6
1.3
0.6
0.6
0.6
Note 2
0
−
0
−
High-Speed Mode
Note 4
Note 5
Note 5
Rmax.
+ t
SU
0.9
MAX.
400
300
300
400
:
50
DAT
−
−
−
−
−
−
−
−
Note 3
= 1,000 + 250
IHmin.
.
of SCL
Unit
kHz
pF
µ
µ
µ
µ
µ
µ
µ
ns
ns
ns
µ
ns
s
s
s
s
s
s
s
s
527