UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 305

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.3 Control Registers
(1) Asynchronous serial interface mode register n (ASIMn)
The ASIMn register is an 8-bit register that controls the UARTn transfer operation.
This register can be read or written in 8-bit or 1-bit units.
This register is set to 01H after reset.
Caution When using UARTn, be sure to set the external pins related to UARTn functions to the
(n = 0, 1)
control mode before setting clock select register n (CKSRn) and baud rate generator control
register n (BRGCn), and then set the UARTCAEn bit to 1. Then set the other bits.
ASIMn
After reset:
UARTCAEn
UARTCAEn
• If UARTCAEn = 0, UARTn is asynchronously reset.
• If UARTCAEn = 0, UARTn is reset. To operate UARTn, first set UARTCAEn to 1.
• If the UARTCAEn bit is changed from 1 to 0, all the registers of UARTn are
• The output of the TXDn pin goes high when transmission is disabled, regardless
• Set the TXEn bit to 1 after setting the UARTCAEn bit to 1 at startup. Set the
• To initialize the transmission unit, clear (0) the TXEn bit, and after letting 2 Clock
TXEn
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
initialized. To set UARTCAEn to 1 again, be sure to re-set the registers of
UARTn.
of the setting of the UARTCAEn bit.
UARTCAEn bit to 0 after setting the TXEn bit to 0 to stop.
cycles (base clock) elapse, set (1) the TXEn bit again. If the TXEn bit is not set
again, initialization may not be successful. (For details of the base clock, refer to
13.6 (1) (a) Base clock (Clock).)
0
1
<7>
0
1
01H
Disables transmission
Enables transmission
Stops clock supply to UARTn.
Supplies clock to UARTn.
R/W
TXEn
<6>
Address: ASIM0
User’s Manual U15905EJ2V1UD
RXEn
<5>
Enables/disables transmission
Controls the operating clock
PSn1
4
FFFFFA00H, ASIM1 FFFFFA10H
PSn0
3
CLn
2
SLn
1
ISRMn
0
(1/3)
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