UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 285

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UPD70F3201YGC-YEU-A

Manufacturer Part Number
UPD70F3201YGC-YEU-A
Description
MCU 32BIT I2C 100TQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Sx2r
Datasheet

Specifications of UPD70F3201YGC-YEU-A

Core Processor
RISC
Core Size
32-Bit
Speed
20MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
68
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 2.7 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3201YGC-YEU-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note When PRSM = 10H, PRSCM = 03H (Refer to 6.5 Prescaler 3.)
Cautions 1. Set the A/D conversion time within the range of 8.2 to 150
Note When PRSM = 10H, PRSCM = 03H (Refer to 6.5 Prescaler 3.)
FR3
FR3
0
0
0
0
0
0
0
0
Other than above
Other than above
FR2
FR2
Table 11-2. Example of Setting A/D Conversion Time (Immediately After Setting ADCS Bit to 1)
0
0
0
0
0
0
0
0
2. Clear the FR3 and FR2 bits to 00.
Table 11-3. Example of Setting A/D Conversion Time (Second and Subsequent Time)
this range is exceeded.
FR1
FR1
0
0
1
1
0
0
1
1
FR0 A/D Conversion
FR0 A/D Conversion
0
1
0
1
0
1
0
1
320/f
160/f
80/f
120/f
392/f
196/f
98/f
147/f
XX
XX
Time
Time
XX
XX
XX
XX
XX
XX
Note
Note
CHAPTER 11 A/D CONVERTER
19.6
9.8
Setting prohibited Setting prohibited Setting prohibited 12.3
Setting prohibited 8.7
16.0
8.0
Setting prohibited Setting prohibited Setting prohibited 10
Setting prohibited 7.1
f
f
XX
XX
User’s Manual U15905EJ2V1UD
µ
µ
= 20 MHz
= 20 MHz
µ
µ
s
s
s
s
18.9
9.5
23.1
11.6
f
f
XX
XX
µ
µ
µ
= 17 MHz
= 17 MHz
µ
s
s
µ
µ
s
s
s
s
Setting prohibited
Setting prohibited
23.8
11.9
8.9
29.1
14.6
10.9
f
f
XX
XX
= 13.5 MHz
= 13.5 MHz
µ
µ
µ
µ
µ
µ
µ
s
s. The operation is not guaranteed if
s
s
s
s
s
49
24.5
18.4
40
20
15
f
f
XX
XX
µ
µ
µ
µ
µ
s
s
s
s
s
= 8 MHz
= 8 MHz
µ
µ
µ
s
s
s
Setting prohibited
98
49
73.5
Setting prohibited
80
40
60
f
f
XX
XX
µ
µ
µ
µ
µ
s
s
s
s
s
= 2 MHz
= 2 MHz
µ
s
283

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