UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 14

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 15 I
CHAPTER 16 DMA FUNCTIONS (DMA CONTROLLER) ................................................................. 408
12
14.2 Configuration ......................................................................................................................... 334
14.3 Control Registers................................................................................................................... 336
14.4 Operation................................................................................................................................ 342
14.5 Output Pins ............................................................................................................................ 345
14.6 System Configuration Example ........................................................................................... 346
15.1 Features.................................................................................................................................. 347
15.2 Configuration ......................................................................................................................... 351
15.3 Control Registers................................................................................................................... 353
15.4 I
15.5 I
15.6 I
15.7 Interrupt Request (INTIIC) Generation Timing and Wait Control...................................... 390
15.8 Address Match Detection Method ....................................................................................... 391
15.9 Error Detection....................................................................................................................... 391
15.10 Extension Code..................................................................................................................... 391
15.11 Arbitration.............................................................................................................................. 392
15.12 Wakeup Function .................................................................................................................. 394
15.13 Communication Reservation ............................................................................................... 395
15.14 Cautions................................................................................................................................. 398
15.15 Communication Operations................................................................................................. 399
15.16 Timing of Data Communication........................................................................................... 401
16.1 Features.................................................................................................................................. 408
16.2 Configuration ......................................................................................................................... 409
16.3 Control Registers................................................................................................................... 410
16.4 DMA Bus States ..................................................................................................................... 417
16.5 Transfer Mode ........................................................................................................................ 419
16.6 Transfer Types ....................................................................................................................... 419
14.1.1
14.1.2
15.1.1
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.4.1
16.4.2
16.5.1
16.6.1
2
2
2
C Bus Mode Functions........................................................................................................ 364
C Bus Definitions and Control Methods ........................................................................... 365
C Interrupt Request (INTIIC) ............................................................................................... 372
2
C BUS .......................................................................................................................... 347
Switching modes between CSI0 and I
Switching modes between CSI1 and UART0 ............................................................................334
Switching modes between I
DMA source address registers 0 to 3 (DSA0 to DSA3) .............................................................410
DMA destination address registers 0 to 3 (DDA0 to DDA3) ......................................................411
DMA byte count registers 0 to 3 (DBC0 to DBC3) .....................................................................412
DMA addressing control registers 0 to 3 (DADC0 to DADC3) ...................................................413
DMA channel control registers 0 to 3 (DCHC0 to DCHC3)........................................................414
DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) .............................................................415
Types of bus states ...................................................................................................................417
DMAC bus cycle state transition................................................................................................418
Single transfer mode .................................................................................................................419
Two-cycle transfer .....................................................................................................................419
User’s Manual U15905EJ2V1UD
2
C and CSI0 ...................................................................................348
2
C ...................................................................................333