UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 306

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

304
Remarks 1. When reception is disabled, the receive shift register does not detect a start bit. No shift-in
2. (Even parity)
processing or transfer processing to receive buffer register n (RXBn) is performed, and the
contents of the RXBn register are retained.
When reception is enabled, the receive shift operation starts, synchronized with the detection of
the start bit, and when the reception of one frame is completed, the contents of the receive shift
register are transferred to the RXBn register. A reception completion interrupt (INTSRn) is also
generated in synchronization with the transfer to the RXBn register.
If the transmit data contains an odd number of bits with the value “1”, the parity bit is set (1). If it
contains an even number of bits with the value “1”, the parity bit is cleared (0). This controls the
number of bits with the value “1” contained in the transmit data and the parity bit so that it is an
even number.
During reception, the number of bits with the value “1” contained in the receive data and the parity
bit is counted, and if the number is odd, a parity error is generated.
(Odd parity)
In contrast to even parity, odd parity controls the number of bits with the value “1” contained in the
transmit data and the parity bit so that it is an odd number.
During reception, the number of bits with the value “1” contained in the receive data and the parity
bit is counted, and if the number is even, a parity error is generated.
(0 parity)
During transmission, the parity bit is cleared (0) regardless of the transmit data.
During reception, no parity error is generated because no parity bit is checked.
(No parity)
No parity bit is added to transmit data.
During reception, the receive data is considered to have no parity bit. No parity error is generated
because there is no parity bit.
• Set the RXEn bit to 1 after setting the UARTCAEn bit to 1 at startup. Set the
• To initialize the reception unit status, clear (0) the RXEn bit, and after letting 2
• To overwrite the PS1 and PS0 bits, first clear (0) the TXEn and RXEn bits.
• If “0 parity” is selected for reception, no parity judgment is performed. Therefore,
RXEn
PSn1
UARTCAEn bit to 0 after setting the RXEn bit to 0 to stop.
Clock cycles (base clock) elapse, set (1) the RXEn bit again. If the RXEn bit is
not set again, initialization may not be successful. (For details of the base clock,
refer to 13.6 (1) (a) Base clock (Clock).)
no error interrupt is generated because the PE bit of the ASISn register is not
set.
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
0
1
0
0
1
1
Disables reception
Enables reception
PSn0
0
1
0
1
Parity bit not output
Output 0 parity
Output odd parity
Output even parity
User’s Manual U15905EJ2V1UD
Transmit operation
Enables/disables reception
Receive with no parity
Receive as 0 parity
Judge as odd parity
Judge as even parity
Receive operation
(2/3)