UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 208

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Examples of settings to change between the main clock and subclock are shown below
(a) Example of setting when changing from main clock to subclock
(b) Example of setting when changing subclock to main clock
<1> Checking internal system clock: Check if the following condition is satisfied.
<2> CK3 bit ← “1”:
<3> Subclock operation:
<4> MCK ← “1”:
<1> MCK ← “0”:
<2> Software wait:
<3> CK3 ← “0”:
<3> Main clock operation: The following time is required between when the CK3 bit is set and when the
CHAPTER 6 CLOCK GENERATION FUNCTION
Oscillation of the main clock is started.
Insert wait states by program and wait until the oscillation stabilization time of
the main clock elapses.
Use of a bit manipulation instruction is recommended. Do not change the
setting of the CK2 to CK0 bits.
main clock specified by the CK2 to CK0 bits is selected.
• Maximum: (1/Subclock frequency)
Therefore, read the CLS bit and confirm that the main clock operation has
started.
User’s Manual U15905EJ2V1UD
• Internal system clock (f
If this condition is not satisfied, change the setting of the CK2 to
CK0 bits so that the condition is satisfied. At this time, do not
change the setting of the CK3 bit.
Use of a bit manipulation instruction is recommended.
change the setting of the CK2 to CK0 bits.
The following time is required between when the CK3 bit is set and
when the subclock operation is started:
• Maximum: (1/Subclock frequency)
Therefore, read the CLS bit and confirm that the subclock operation
has started.
Set MCK to 1 only when stopping the main clock.
CLK
) > Subclock (32.768 kHz) × 4
Do not