UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 253

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.4.4
PWM output.
TOn pin.
TMCn1 bit of the TMCn register.
By setting the TMCn6 bit of 8-bit timer mode control register n (TMCn) to 1, 8-bit timer/event counter n performs
Pulses with the duty factor determined by the value set in 8-bit timer compare register n (CRn) are output from the
Set the width of the active level of the PWM pulse in the CRn register. The active level can be selected using the
The count clock can be selected using timer clock selection register n (TCLn).
PWM output can be enabled/disabled by the TOEn bit of the TMCn register.
Caution The CRn register rewrite interval must be three or more operation clocks (set by the TCLn
(1) Basic operation of PWM output
8-bit PWM output operation
Setting method
PWM output operation
<1> Set each register.
<2> When the TMCEn bit of the TMCn register is set to 1, counting starts.
<1> When counting starts, PWM output (output from the TOn pin) outputs the inactive level until an
<2> When an overflow occurs, the active level set by setting method <1> is output. The active level is
<3> When the value of the CRn register and the count value match, the inactive level is output and
<4> Then, steps <2> and <3> are repeated until counting is stopped.
<5> When counting is stopped by setting TMCEn to 0, PWM output becomes inactive.
register).
• TCLn register: Selects the count clock (t).
• CRn register:
• TMCn register: Stops count operation, selects PWM mode, and leave timer output F/F unchanged.
overflow occurs.
output until the value of the CRn register and the count value of 8-bit timer counter n (TMn) match.
continues to be output until an overflow occurs again.
Remark
n = 2 to 5
Cycle = 2
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 2 TO 5
Compare value (N)
TMCn1
8
Timer output enabled
(TMCn register = 01000001B or 01000011B)
t, active level width = Nt, duty = N/2
0
1
Active high
Active low
User’s Manual U15905EJ2V1UD
Active Level Selection
8
: N = 00 to FFH
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