UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 278

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.3 Oscillation stabilization time selection function
stabilization time register (OSTS).
276
The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the oscillation
The OSTS register is set by an 8-bit memory manipulation instruction.
This register is set to 04H after reset.
Cautions 1. The wait time following release of the software STOP mode does not include the time until
Remark
2. Be sure to set bits 3 to 7 to 0.
3. Set the oscillation stabilization time to 1.5 ms or longer.
4. The oscillation stabilization time following reset release is 2
f
X
= Main clock oscillation frequency
OSTS
After reset:
the clock oscillation starts (“a” in the figure below) following release of the software STOP
mode, regardless of whether the STOP mode is released by reset or the occurrence of an
interrupt request signal.
of the OSTS register = 04H).
OSTS2
04H
0
0
0
0
1
1
1
1
0
Voltage waveform of X1 pin
CHAPTER 10 WATCHDOG TIMER FUNCTIONS
R/W
OSTS1
0
0
0
1
1
0
0
1
1
Address:
OSTS0
User’s Manual U15905EJ2V1UD
0
0
1
0
1
0
1
0
1
V
SS
FFFFF6C0H
2
2
2
2
2
2
2
2
STOP mode release
14
16
17
18
19
20
21
22
/f
/f
/f
/f
/f
/f
/f
/f
0
X
X
X
X
X
X
X
X
Selection of oscillation stabilization time
Setting
prohibited
3.28 ms
6.55 ms
13.1 ms
26.2 ms
52.4 ms
20 MHz
105 ms
210 ms
a
0
3.855 ms
7.710 ms
15.42 ms
30.84 ms
61.68 ms
123.4 ms
246.7 ms
Setting
prohibited
OSTS2
17 MHz
f
X
13.5 MHz
4.855 ms
9.709 ms
19.42 ms
38.84 ms
77.67 ms
155.3 ms
310.7 ms
Setting
prohibited
19
OSTS1
/f
X
(because the initial value
2.048 ms
8.192 ms
16.38 ms
32.77 ms
65.54 ms
131.1 ms
262.1 ms
524.3 ms
OSTS0
8 MHz