UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 358

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

356
Note This flag’s signal is invalid when IICE = 0.
Remark
Cautions concerning set timing
• For master reception: Cannot be set during transfer. Can be set only when ACKE has been set to 0
• For master transmission: A start condition cannot be generated normally during the ACK period. Set
• Cannot be set at the same time as SPT
Condition for clearing (STT = 0)
• Cleared by instruction
• Cleared by loss in arbitration
• Cleared after start condition is generated by
• When LREL = 1
• When IICE = 0
• After reset
Condition for clearing (ACKE = 0)Note
• Cleared by instruction
• After reset
ACKE
and slave has been notified of final reception.
during the wait period.
STT
master device
Bit 1 (STT) is 0 if it is read immediately after data setting.
0
1
0
1
Acknowledgment disable.
Acknowledgment enabled. During the ninth clock period, the SDA line is set to low level.
However, ACK is invalid during address transfers and is valid when EXC = 1.
Start condition not generated.
When bus is released (in STOP mode):
When bus is not used:
In the wait state (when master device):
Generates a start condition (for starting as master). The SDA line is changed from high level
to low level and then the start condition is generated. Next, after the rated amount of time has
elapsed, SCL is changed to low level.
This trigger functions as a start condition reserve flag. When set, it releases the bus and then
automatically generates a start condition.
Generates a restart condition after releasing the wait.
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Start condition trigger
Acknowledge control
Condition for setting (STT = 1)
• Set by instruction
Condition for setting (ACKE = 1)
• Set by instruction
2
C BUS
(3/4)