UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 318

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

316
• Set transmission mode
• Write data (1)
• Read ASIFn register (confirm that TXBFn bit = 0)
• Write data (2)
• Read ASIFn register (confirm that TXBFn bit = 0)
• Write data (3)
• Read ASIFn register (confirm that TXBFn bit = 0)
• Write data (4)
(TXBFn, TXSFn bits)
Note Transition period
Note Since this period is a transition period from 10 to 01, when reading the TXBFn and TXSFn bits of the
INTSTn (output)
(a) Starting procedure
ASIFn register
TXDn (output)
TXSn register
TXBn register
ASIFn register simultaneously, 11 or 00 may be read. Thus, whether writing to the TXBn register is
enabled or not should be judged only for the TXBFn bit.
Transmission Starting Procedure
The procedure to start continuous transmission is shown below.
<1>
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE n (UARTn)
FFH
Figure 13-6. Continuous Transmission Starting Procedure
00
FFH
10
Note
Start
Data (1)
bit
<2>
User’s Manual U15905EJ2V1UD
01
Data (1)
<1> Start transmission unit
<2> Generate start bit
Start data (1) transmission
<3> INTSTn interrupt occurs
<4> Generate start bit
<5> INTSTn interrupt occurs
Data (1)
Start data (2) transmission
<<Transmission in progress>>
<<Transmission in progress>>
Data (2)
11
Internal Operation
<3>
01
Stop
bit
Start
bit
<4>
Data (2)
11
Data (2)
Data (3)
TXBFn
ASIFn Register
0
1
1
0
0
1
0
0
1
0
0
1
0
<5>
01
Stop
Data (3)
bit
TXSFn
1/0
1/0
11
0
0
1
1
1
1
1
1
1
1
1
Note
Note