UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 430

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.2 Non-Maskable Interrupts
disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts.
edge detection”.
and WDTM3 bits of the watchdog timer mode register (WDTM) are set to “10”.
follows (the interrupt with the lower priority is ignored).
428
A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt
This product has the following two non-maskable interrupts.
• NMI pin input (NMI)
• Non-maskable interrupt request generated by overflow of watchdog timer (INTWDT)
The valid edge of the NMI pin can be selected from four types: “rising edge”, “falling edge”, “both edges”, and “no
The non-maskable interrupt generated by overflow of the watchdog timer (INTWDT) functions when the WDTM4
If two or more non-maskable interrupts occur at the same time, the interrupt with the higher priority is serviced, as
INTWDT > NMI
If a new NMI or INTWDT request is issued while a NMI is being serviced, it is serviced as follows.
(1) If new NMI request is issued while NMI is being serviced
(2) If INTWDT request is issued while NMI is being serviced
Caution If a non-maskable interrupt request is generated, the values of the PC and PSW are saved to the
The new NMI request is held pending, regardless of the value of the NP bit of the program status word (PSW)
in the CPU. The pending NMI interrupt is acknowledged after the NMI currently under execution has been
serviced (after the RETI instruction has been executed).
The INTWDT request is held pending if the NP bit of the PSW remains set (1) while the NMI is being serviced.
The pending INTWDT request is acknowledged after the NMI currently under execution has been serviced
(after the RETI instruction has been executed).
If the NP bit of PSW is cleared (0) while the NMI is being serviced, the newly generated INTWDT request is
executed (the NMI servicing is stopped).
NMI status save registers (FEPC and FEPSW). At this time, execution can be returned by the
RETI instruction only from an NMI.
serviced. Therefore, reset the system after the interrupt has been serviced.
Figure 17-1. Non-Maskable Interrupt Request Acknowledgment Operation (1/2)
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(a) NMI and INTWDT requests generated at the same time
NMI and
(generated simultaneously)
INTWDT requests
User’s Manual U15905EJ2V1UD
Main routine
Execution cannot be returned while INTWDT is being
System reset
INTWDT servicing