UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 235

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) One-shot pulse output
Remarks 1. 0/1: Set to 0 or 1 as necessary
TMCn0
TMCn1
By setting the TMCn0 and TMCn1 registers as shown in Figure 7-13, the 16-bit timer/event counter can output
a one-shot pulse from the TOn pin by using the valid edge of the TCLRn pin as an external trigger.
The valid edge of the TCLRn pin is selected according to the CESn0 and CESn1 bits of the SESn register. The
rising edge, falling edge, or both rising and falling edges can be selected as the valid edge of both pins.
The TMn register is cleared and started by setting a valid edge to the TCLRn pin. TOn output becomes active
at the count value set in advance to the CCn0 register. After that, the TOn output becomes inactive at the
count value set in advance to CCn1 register. The active level of the TOn output can be set by the ALVn bit of
the TMCn1 register. When the setting value of the CCn0 register and the setting value of the CCn1 register
are the same, the TOn output remains inactive and does not change.
The active level of the TOn output can be set by the ALVn bit of the TMCn1 register.
Remark
2. n = 0, 1
OVFn
OSTn ENTOn ALVn
0/1
1
n = 0, 1
CSn2 CSn1 CSn0
When 16-Bit Timer/Event Counter Is Used for One-Shot Pulse Output
0/1
1
0/1
0/1
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 0 AND 1
ETIn CCLRnECLRn CMSn1 CMSn0
Figure 7-13. Contents of Register Settings
0/1
0/1
0
0
User’s Manual U15905EJ2V1UD
0
1
TMCEn TMCAEn
1
1
1
1
Supply input clocks to internal units
Enable count operation
Use CCn0 register as compare register
Use CCn1 register as compare register
Enable clearing of TMn register by TCLRn
input
Disable clearing of TMn reigster due to
match with CCn0 register
Enable external pulse output (TOn)
Timer holds 0000H and stops counting after
TMn register overflows
233