UPD70F3201YGC-YEU-A Renesas Electronics America, UPD70F3201YGC-YEU-A Datasheet - Page 359

• Manufacturer Part Number: UPD70F3201YGC-YEU-A
• Description: MCU 32BIT I2C 100TQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Sx2r

Specifications of UPD70F3201YGC-YEU-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 2.7 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note Set SPT only in master mode. However, SPT must be set and a stop condition generated before the first
Caution When bit 3 (TRC) of the IIC status register (IICS) is set to 1, WREL is set during the ninth clock
Remark
stop condition is detected following the switch to the operation enabled status. For details, see 15.14
Cautions.
Condition for clearing (SPT = 0)
• Cleared by instruction
• Cleared by loss in arbitration
• Automatically cleared after stop condition is
• When LREL = 1
• When IICE = 0
• After reset
Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the ACK period. Set
• Cannot be set at the same time as STT.
• SPT can be set only when in master mode
• When WTIM has been set to 0, if SPT is set during the wait period that follows output of eight clocks,
SPT
detected
note that a stop condition will be generated during the high-level period of the ninth clock.
When a ninth clock must be output, WTIM should be changed from 0 to 1 during the wait period
following output of eight clocks, and SPT should be set during the wait period that follows output of the
ninth clock.
and wait is canceled, after which TRC is cleared and the SDA line is set to high impedance.
Bit 0 (SPT) is 0 if it is read immediately after data setting.
0
1
Stop condition is not generated.
Stop condition is generated (termination of master deviceÕs transfer).
After the SDA line goes to low level, either set the SCL line to high level or wait until it goes to
high level. Next, after the rated amount of time has elapsed, the SDA line is changed from low l
evel to high level and a stop condition is generated.
Cannot be set during transfer.
Can be set only when ACKE has been set to 0 and during the wait period after
slave has been notified of final reception.
during the wait period.
User’s Manual U15905EJ2V1UD
CHAPTER 15 I
Note
.
Stop condition trigger
Condition for setting (SPT = 1)
• Set by instruction
2
C BUS
(4/4)
357