R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 940
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Section 24 Power-Down Modes
24.8.3
In deep software standby mode, the ports retain the states that were held during software standby
mode. The internal of the LSI is initialized by an internal reset caused by deep software standby
mode, and the reset exception handling starts as soon as deep software standby mode is canceled.
The following shows the port states at this time.
(1)
Pins for the address bus, bus control signals (CS0, AS, HWR and LWR), and data bus operate
depending on the CPU.
(2)
Whether the ports are initialized or retain the states that were held during software standby mode
can be selected by the IOKEEP bit.
• When IOKEEP = 0
• When IOKEEP = 1
24.8.4
When the IOKEEP bit is 0, Bφ output is undefined for a maximum of one cycle immediately after
exit from deep software standby mode. At this time, the output state cannot be guaranteed. Even
when the IOKEEP bit is set to 1, Bφ output is undefined for a maximum of one cycle immediately
after the IOKEEP bit is cleared to 0 after deep software standby mode was canceled, and the
output state cannot be guaranteed. (See figure 24.3)
However, clock can be normally output by canceling deep software standby mode with the
IOKEEP bit set to 1 and then controlling the Bφ output with the IOKEEP and PSTOP1 bits. Use
the following procedure.
Rev. 2.00 Sep. 16, 2009 Page 910 of 1036
REJ09B0414-0200
Ports are initialized by an internal reset caused by deep software standby mode.
The port states that were held in deep software standby mode are retained regardless of the LSI
internal state though the internal of the LSI is initialized by an internal reset caused by deep
software standby mode. At this time, the port states that were held in software standby mode
are retained even if settings of I/O ports or peripheral modules are set. Subsequently, the
retained port states are released when the IOKEEP bit is cleared to 0 and operation is
performed according to the internal settings.
Pins for address bus, bus control and data bus
Pins other than address bus, bus control and data bus pins
Pin State on Exit from Deep Software Standby Mode
Bφ Operation after Exit from Deep Software Standby Mode
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