R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 302

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 9 DMA Controller (DMAC)
Rev. 2.00 Sep. 16, 2009 Page 272 of 1036
REJ09B0414-0200
Bit
30
29
28
27
26
25, 24
23
22 to 20 
Bit Name
DACKE
TENDE
DREQS
NRD
ACT
Initial
Value
0
0
0
0
0
All 0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Description
DACK Signal Output Enable
Enables/disables the DACK signal output in single
address mode. This bit is ignored in dual address mode.
0: Enables DACK signal output
1: Disables DACK signal output
TEND Signal Output Enable
Enables/disables the TEND signal output.
0: Enables TEND signal output
1: Disables TEND signal output
Reserved
Initial value should not be changed.
DREQ Select
Selects whether a low level or the falling edge of the
DREQ signal used in external request mode is detected.
When a block transfer is performed in external request
mode, clear this bit to 0.
0: Low level detection
1: Falling edge detection (the first transfer after a
Next Request Delay
Selects the accepting timing of the next transfer request.
0: Starts accepting the next transfer request after
1: Starts accepting the next transfer request one cycle
Reserved
These bits are always read as 0 and cannot be
modified.
Active State
Indicates the operating state for the channel.
0: Waiting for a transfer request or a transfer disabled
1: Active state
Reserved
These bits are always read as 0 and cannot be
modified.
transfer enabled is detected on a low level)
completion of the current transfer
after completion of the current transfer
state by clearing the DTE bit to 0

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