R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 351

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Figure 9.32 shows an example of block transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the write cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
DREQ
Address bus
DMA
operation
Channel
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the write cycle.
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the Bφ signal and a transfer request is held. This is the same as [1].)
Wait
Figure 9.32 Example of Transfer in Block Transfer Mode Activated
[1]
Request
Min. of 3 cycles
Bus released
[2]
Read
[3]
Duration of transfer
request disabled
DMA read
Transfer
source
cycle
1-block transfer
Write
by DREQ Low Level
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
[4]
Request
Min. of 3 cycles
Bus released
[5]
Rev. 2.00 Sep. 16, 2009 Page 321 of 1036
Read
[6]
Section 9 DMA Controller (DMAC)
Duration of transfer
DMA read
request disabled
Transfer
cycle
source
1-block transfer
Write
Transfer request enable resumed
DMA write
destination
Transfer
cycle
Wait
REJ09B0414-0200
[7]
Bus released

Related parts for R0K561622S000BE