R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 369

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by
an interrupt request.
10.1
• Transfer possible over any number of channels:
• Three transfer modes
• Short address mode or full address mode selectable
• Size of data for data transfer can be specified as byte, word, or longword
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Read skip of the transfer information specifiable
• Writeback skip executed for the fixed transfer source and destination addresses
• Module stop state specifiable
Multiple data transfer enabled for one activation source (chain transfer)
Chain transfer specifiable after data transfer (when the counter is 0)
Normal/repeat/block transfer modes selectable
Transfer source and destination addresses can be selected from increment/decrement/fixed
 Short address mode
 Full address mode
The bus cycle is divided if an odd address is specified for a word or longword transfer.
The bus cycle is divided if address 4n + 2 is specified for a longword transfer.
A CPU interrupt can be requested after one data transfer completion
A CPU interrupt can be requested after the specified data transfer completion
Transfer information is located on a 3-longword boundary
The transfer source and destination addresses can be specified by 24 bits to select a 16-
Mbyte address space directly
Transfer information is located on a 4-longword boundary
The transfer source and destination addresses can be specified by 32 bits to select a 4-
Gbyte address space directly
Features
Section 10 Data Transfer Controller (DTC)
Rev. 2.00 Sep. 16, 2009 Page 339 of 1036
Section 10 Data Transfer Controller (DTC)
REJ09B0414-0200