R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 934

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 24 Power-Down Modes
24.7
24.7.1
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1 and the DPSBY bit in
DPSBYCR is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip
peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers,
on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, and the states
of the I/O ports, are retained. Whether the address bus and bus control signals are placed in the
high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this
mode the oscillator stops, allowing power consumption to be significantly reduced.
If the WDT is used in watchdog timer mode, it is impossible to make a transition to software
standby mode. The WDT should be stopped before the SLEEP instruction execution.
24.7.2
Software standby mode is cleared by an external interrupt (NMI, or IRQ0 to IRQ15*) or by means
of the RES pin or STBY pin.
1. Exit from software standby mode by interrupt
2. Exit from software standby mode by RES pin
3. Exit from software standby mode by STBY pin
Rev. 2.00 Sep. 16, 2009 Page 904 of 1036
REJ09B0414-0200
When an NMI, or IRQ0 to IRQ15* interrupt request signal is input, clock oscillation starts,
and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied
to the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ11* interrupt, set the
corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts
IRQ0 to IRQ11* is generated. Software standby mode cannot be cleared if the interrupt has
been masked on the CPU side or has been designated as a DTC activation source.
Note: * By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ15 can be used as a software
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception
handling.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Software Standby Mode
Entry to Software Standby Mode
Exit from Software Standby Mode
standby mode clearing source.

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