R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 899
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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Section 23 Clock Pulse Generator
Section 23 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (Iφ),
peripheral module clock (Pφ), external bus clock (Bφ), and ∆Σ A/D converter clock (Aφ). The
clock pulse generator comprises an oscillator, frequency dividers, PLL (phase-locked loop) circuit,
and selectors. Figure 23.1 is a block diagram of the clock pulse generator.
This LSI supports four clocks: a system clock supplied to the CPU and bus masters, a peripheral
module clock supplied to the peripheral modules, an external bus clock supplied to the external
bus, and a ∆Σ A/D clock supplied to the ∆Σ A/D converter. The clock frequencies can be changed
by the frequency dividers, PLL circuit, and selectors. The frequencies of the system clock,
peripheral module clock and external bus clock are changed the by setting the system clock
control register (SCKCR) by software. The ∆Σ A/D converter clock is generated from the
oscillator output multiplied by 8, the frequency of which can be changed by setting the ∆Σ A/D
mode register (DSADMR) by software.
Frequencies of the peripheral module clock, the external bus clock, and the system clock can be
set independently, although the peripheral module clock and the external bus clock only operate at
frequencies lower than the system clock frequency. Since the ∆Σ A/D converter has been designed
to deliver the maximum precision at approximately 25 MHz, the division ratio for the ∆Σ A/D
converter clock should be set in DSADMR so as to make the frequency near 25 MHz.
Rev. 2.00 Sep. 16, 2009 Page 869 of 1036
REJ09B0414-0200
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