R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 23

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
16.4
16.5
16.6
16.7
16.8
16.9
16.3.10 Serial Extended Mode Register_2 (SEMR_2) .................................................. 635
Operation in Asynchronous Mode .................................................................................... 637
16.4.1
16.4.2
16.4.3
16.4.4
16.4.5
16.4.6
Multiprocessor Communication Function......................................................................... 648
16.5.1
16.5.2
Operation in Clocked Synchronous Mode ........................................................................ 654
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
Operation in Smart Card Interface Mode.......................................................................... 662
16.7.1
16.7.2
16.7.3
16.7.4
16.7.5
16.7.6
16.7.7
16.7.8
Interrupt Sources............................................................................................................... 673
16.8.1
16.8.2
Usage Notes ...................................................................................................................... 675
16.9.1
16.9.2
16.9.3
16.9.4
16.9.5
16.9.6
16.9.7
Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ......................................................................................... 639
Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode)........................................................................... 660
Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).................................................................. 675
Data Transfer Format........................................................................................ 638
Clock................................................................................................................. 640
SCI Initialization (Asynchronous Mode) .......................................................... 641
Serial Data Transmission (Asynchronous Mode) ............................................. 642
Serial Data Reception (Asynchronous Mode)................................................... 644
Multiprocessor Serial Data Transmission ......................................................... 650
Multiprocessor Serial Data Reception .............................................................. 651
Clock................................................................................................................. 654
SCI Initialization (Clocked Synchronous Mode) .............................................. 655
Serial Data Transmission (Clocked Synchronous Mode) ................................. 656
Serial Data Reception (Clocked Synchronous Mode)....................................... 658
Sample Connection ........................................................................................... 662
Data Format (Except in Block Transfer Mode) ................................................ 663
Block Transfer Mode ........................................................................................ 664
Receive Data Sampling Timing and Reception Margin.................................... 665
Initialization ...................................................................................................... 666
Data Transmission (Except in Block Transfer Mode) ...................................... 667
Serial Data Reception (Except in Block Transfer Mode).................................. 670
Clock Output Control........................................................................................ 671
Interrupts in Normal Serial Communication Interface Mode ........................... 673
Interrupts in Smart Card Interface Mode .......................................................... 674
Module Stop Function Setting .......................................................................... 675
Break Detection and Processing ....................................................................... 675
Mark State and Break Detection ....................................................................... 675
Relation between Writing to TDR and TDRE Flag .......................................... 676
Restrictions on Using DTC or DMAC.............................................................. 676
SCI Operations during Mode Transitions ......................................................... 677
Rev. 2.00 Sep. 16, 2009 Page xxi of xxviii

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