R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 280

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 8 Bus Controller (BSC)
8.11.3
Figure 8.43 shows the timing for transition to the bus released state.
Rev. 2.00 Sep. 16, 2009 Page 250 of 1036
REJ09B0414-0200
[1] A low level of the BREQ signal is sampled at the rising edge of the Bφ signal.
[2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or
[3] The BACK signal is driven low, releasing bus to the external bus master.
[4] The BREQ signal state sampling is continued in the external bus released state.
[5] A high level of the BREQ signal is sampled.
[6] The external bus released cycles are ended one cycle after the BREQ signal is driven high.
[7] When the external space is accessed by an internal bus master during external bus released while the BREQOE
[8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Address bus
Data bus
CSn
AS
RD
LHWR, LLWR
BREQ
BACK
BREQO
more after the low level of the BREQ signal is sampled.
bit is set to 1, the BREQO signal goes low.
Transition Timing
Figure 8.43 Bus Released State Transition Timing
External space
access cycle
[1]
T
1
T
2
[2]
[3]
[4]
External bus released state
[7]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[5]
[8]
[6]
CPU cycle

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