R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 273

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
(4)
If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set
to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external
access (n = 0 to 7).
Figure 8.40 shows an example of the operation in this case. In this example, bus cycle A is a
single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is
not inserted, and a conflict occurs in bus cycle B between the external device write data and this
LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Figure 8.40 Example of Idle Cycle Operation (Write after Single Address Transfer Write)
Address bus
CS (area A)
CS (area B)
LLWR
DACK
Data bus
External Access after Single Address Transfer Write
(a) No idle cycle inserted
Bus cycle A
T
1
(IDLS3 = 0)
T
2
Output floating
time is long.
T
3
Bus cycle B
T
1
T
2
Data conflict
Rev. 2.00 Sep. 16, 2009 Page 243 of 1036
T
Bus cycle A
1
(IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0)
T
2
(b) Idle cycle inserted
Section 8 Bus Controller (BSC)
T
3
T
Bus cycle B
i
REJ09B0414-0200
T
1
T
2

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