R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 178

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 7 User Break Controller (UBC)
7.3.3
BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels
A, B, C, and D of the UBC.
Rev. 2.00 Sep. 16, 2009 Page 148 of 1036
REJ09B0414-0200
Bit
15
14
13
12
11
10
9
8
7
6
Initial Value:
[Legend]
n = Channels A to D
R/W:
Bit:
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD)
Bit Name
CMFCPn
CPn2
CPn1
CPn0
R/W
15
0
R/W
14
0
CMFCPn
R/W
13
0
Initial
Value
0
0
0
0
0
0
0
0
0
0
R/W
12
0
CPn2
R/W
11
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CPn1
R/W
10
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Condition Match CPU Flag
UBC break source flag that indicates satisfaction of a
specified CPU bus cycle condition.
0: The CPU cycle condition for channel n break
1: The CPU cycle condition for channel n break
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle Select
These bits select CPU cycles as the bus cycle break
condition for the given channel.
000: Break requests will not be generated.
001: The bus cycle break condition is CPU cycles.
01x: Setting prohibited
1xx: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
CPn0
R/W
9
0
requests has not been satisfied.
requests has been satisfied.
R/W
8
0
R/W
7
0
R/W
6
0
IDn1
R/W
5
0
IDn0
R/W
4
0
RWn1
R/W
3
0
RWn0
R/W
2
0
R/W
1
0
R/W
0
0

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