R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 1061

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Numerics
∆Σ A/D converter ................................... 741
0-output/1-output .................................... 483
16-bit access space.................................. 200
16-bit counter mode................................ 579
16-bit timer pulse unit (TPU) ................. 439
8-bit access space.................................... 199
8-bit timers (TMR) ................................. 553
A
A/D conversion accuracy........................ 730
A/D converter ......................................... 715
Absolute accuracy................................... 730
Acknowledge .......................................... 697
Address error ............................................ 93
Address map ............................................. 76
Address modes........................................ 286
Address/data multiplexed
I/O interface.................................... 193, 228
All-module-clock-stop mode .......... 882, 903
Area 0 ..................................................... 194
Area 1 ..................................................... 195
Area 2 ..................................................... 195
Area 3 ..................................................... 196
Area 4 ..................................................... 196
Area 5 ..................................................... 197
Area 6 ..................................................... 198
Area 7 ..................................................... 198
Area division........................................... 188
Asynchronous mode ............................... 637
AT-cut parallel-resonance type............... 875
Average transfer rate generator............... 602
Index
B
Bφ clock output control........................... 924
Basic bus interface .......................... 192, 202
Big endian ............................................... 191
Bit rate..................................................... 625
Bit synchronous circuit ........................... 712
Block structure ........................................ 782
Block transfer mode ........................ 292, 363
Boot mode....................................... 779, 806
Buffer operation ...................................... 488
Burst access mode................................... 298
Burst ROM interface....................... 192, 223
Bus access modes.................................... 297
Bus arbitration......................................... 254
Bus configuration.................................... 180
Bus controller (BSC)............................... 155
Bus cycle division ................................... 357
Bus width ................................................ 191
Bus-released state...................................... 68
Byte control SRAM interface ......... 192, 215
C
Cascaded connection............................... 579
Cascaded operation ................................. 492
Chain transfer.......................................... 364
Chip select signals................................... 189
Clock pulse generator ............................. 869
Clock synchronization cycle (Tsy).......... 182
Clocked synchronous mode .................... 654
Communications protocol ....................... 839
Compare match A ................................... 577
Compare match B ................................... 578
Compare match count mode ................... 580
Compare match signal............................. 577
Counter operation.................................... 480
Rev. 2.00 Sep. 16, 2009 Page 1031 of 1036
REJ09B0414-0200