R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 165

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
(2)
The DTC activation source is selected according to the default priority, and the selection is not
affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt
Sources, DTC Vector Addresses, and Corresponding DTCEs.
(3)
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the
CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is
selected as the DTC or DMAC activation source or CPU interrupt source, respective operations
are performed independently.
Table 6.6 lists the selection of interrupt sources and interrupt source clear control by setting the
DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERG of the DTC, and the
DISEL bit in MRB of the DTC.
Table 6.6
[Legend]
√: The corresponding interrupt is used. The interrupt source is cleared.
O: The corresponding interrupt is used. The interrupt source is not cleared.
X: The corresponding interrupt is not available.
*: Don't care.
(4)
The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in
table 6.6, when the DTC or DMAC reads/writes the prescribed register.
To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP =
DMAP) should be assigned.
DTA
0
1
DMAC Setting
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
Priority Determination
Operation Order
Usage Note
Interrupt Source Selection and Clear Control
DTCE
0
1
*
DTC Setting
DISEL
*
0
1
*
DMAC
O
O
O
Interrupt Source Selection/Clear Control
Rev. 2.00 Sep. 16, 2009 Page 135 of 1036
DTC
X
O
X
Section 6 Interrupt Controller
REJ09B0414-0200
CPU
X
X

Related parts for R0K561622S000BE