R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 60

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 2 CPU
2.2.3
The data area is extended to 4 Gbytes as compared with that in middle mode.
• Address Space
• Extended Registers (En)
• Instruction Set
• Exception Vector Table and Memory Indirect Branch Addresses
Rev. 2.00 Sep. 16, 2009 Page 30 of 1036
REJ09B0414-0200
The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to
16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated.
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
All instructions and addressing modes can be used.
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower
24 bits are stored. The structure of the exception vector table is shown in figure 2.4.
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes
are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction
code specifies a memory location. Execution branches to the contents of the memory location.
In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch
address. The upper eight bits are reserved and assumed to be H'00.
Advanced Mode
Figure 2.4 Exception Vector Table (Middle and Advanced Modes)
H'00000000
H'00000001
H'00000002
H'00000003
H'00000004
H'00000005
H'00000006
H'00000007
Reset exception vector
Reserved
Reserved
Exception vector table