R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 89

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

2.8
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.12 Addressing Modes
2.8.1
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the
register field in the instruction code.
R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers.
ER0 to ER7 can be specified as 32-bit registers.
No. Addressing Mode
1
2
3
4
5
6
7
8
9
10
11
Register direct
Register indirect
Register indirect with displacement
Index register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Register indirect with pre-increment
Register indirect with post-decrement
Absolute address
Immediate
Program-counter relative
Program-counter relative with index register
Memory indirect
Extended memory indirect
Addressing Modes and Effective Address Calculation
Register Direct—Rn
Symbol
Rn
@ERn
@(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
@(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
@ERn+
@−ERn
@+ERn
@ERn−
@aa:8/@aa:16/@aa:24/@aa:32
#xx:3/#xx:4/#xx:8/#xx:16/#xx:32
@(d:8,PC)/@(d:16,PC)
@(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
@@aa:8
@@vec:7
Rev. 2.00 Sep. 16, 2009 Page 59 of 1036
REJ09B0414-0200
Section 2 CPU