R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 196

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 8 Bus Controller (BSC)
8.2.4
RDNCR selects the negation timing of the read strobe signal (RD) when reading the external
address spaces specified as a basic bus interface or the address/data multiplexed I/O interface.
Notes: 1. In an external address space which is specified as byte control SRAM interface, the
Rev. 2.00 Sep. 16, 2009 Page 166 of 1036
REJ09B0414-0200
Bit
15
14
13
12
11
10
9
8
7 to 0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
2. In an external address space which is specified as burst ROM interface, the RDNCR
Bit Name
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
Read Strobe Timing Control Register (RDNCR)
RDNCR setting is ignored and the same operation when RDNn = 1 is performed.
setting is ignored during CPU read accesses and the same operation when RDNn = 0 is
performed.
RDN7
R/W
15
R
0
7
0
Initial
Value
0
0
0
0
0
0
0
0
All 0
RDN6
R/W
14
R
0
6
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
RDN5
R/W
13
R
0
5
0
Description
Read Strobe Timing Control
RDN7 to RDN0 set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 8.2, the read strobe for an area for
which the RDNn bit is set to 1 is negated one half-
cycle earlier than that for an area for which the RDNn
bit is cleared to 0. The read data setup and hold time
are also given one half-cycle earlier.
0: In an area n read access, the RD signal is negated
1: In an area n read access, the RD signal is negated
(n = 7 to 0)
Reserved
These are read-only bits and cannot be modified.
RDN4
at the end of the read cycle
one half-cycle before the end of the read cycle
R/W
12
R
0
4
0
RDN3
R/W
11
R
0
3
0
RDN2
R/W
10
R
0
2
0
RDN1
R/W
R
9
0
1
0
RDN0
R/W
R
8
0
0
0

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