R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 287
R0K561622S000BE
Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K561622S000BE
Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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8.15
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
8.16
(1)
The BSC registers must be specified before accessing the external address space. In on-chip ROM
disabled mode, the BSC registers must be specified before accessing the external address space for
other than an instruction fetch access.
(2)
In this LSI, if the ACSE bit in MSTPCRA is set to 1, and then a SLEEP instruction is executed
with the setting for all peripheral module clocks to be stopped (MSTPCRA and MSTPCRB =
H'FFFFFFFF) or for operation of the 8-bit timer module alone (MSTPCRA = H'F[E to
0]FFFFFF), and a transition is made to the sleep state, the all-module-clock-stop mode is entered
in which the clock is also stopped for the bus controller and I/O ports. For details, see section 24,
Power-Down Modes.
In this state, the external bus release function is halted. To use the external bus release function in
sleep mode, the ACSE bit in MSTPCR must be cleared to 0. Conversely, if a SLEEP instruction to
place the chip in all-module-clock-stop mode is executed in the external bus released state, the
transition to all-module-clock-stop mode is deferred and performed until after the bus is
recovered.
(3)
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this
mode, indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby mode.
Note that the BACK and BREQO pins are both in the high-impedance state in software standby
mode.
Setting Registers
External Bus Release Function and All-Module-Clock-Stop Mode
External Bus Release Function and Software Standby
Bus Controller Operation in Reset
Usage Notes
Rev. 2.00 Sep. 16, 2009 Page 257 of 1036
Section 8 Bus Controller (BSC)
REJ09B0414-0200
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