R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 281

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.12
8.12.1
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 8.25 shows the number of access cycles for each on-chip memory space.
Table 8.25 Number of Access Cycles for On-Chip Memory Spaces
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
Table 8.26 lists the number of access cycles for registers of on-chip peripheral modules.
Table 8.26 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Access Space
On-chip ROM space
On-chip RAM space
Module to be Accessed
DMAC and UBC registers
MCU operating mode, clock pulse generator,
power-down control registers, interrupt controller,
bus controller, DTC registers
I/O port registers of PFCR and WDT
I/O port registers other than PFCR,
TPU, PPG, TMR, SCI0 to SCI4, and D/A registers
A/D, ∆Σ A/D
Internal Bus
Access to Internal Address Space
Access
Read
Write
Read
Write
Read
Two Iφ
Two Pφ
Number of Cycles
Three Pφ
Two Pφ
Two Iφ
Write
Three Iφ Disabled
Three Pφ Disabled
Rev. 2.00 Sep. 16, 2009 Page 251 of 1036
Three Iφ cycles
One Iφ cycle
Number of Access Cycles
One Iφ cycle
One Iφ cycle
Write Data Buffer Function
Disabled
Enabled
Enabled
Section 8 Bus Controller (BSC)
REJ09B0414-0200