R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 706

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 16 Serial Communication Interface (SCI)
16.9.5
The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written
to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR
yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the
TDRE flag is set to 1.
16.9.6
• When the external clock source is used as a synchronization clock, update TDR by the DTC or
• When using the DTC or DMAC to read RDR, be sure to set the receive end interrupt (RXI) as
Rev. 2.00 Sep. 16, 2009 Page 676 of 1036
REJ09B0414-0200
DMAC and wait for at least five Pφ clock cycles before allowing the transmit clock to be
input. If the transmit clock is input within four clock cycles after TDR modification, the SCI
may malfunction (figure 16.33).
the DTC or DMAC activation source.
Figure 16.33 Sample Transmission using DTC in Clocked Synchronous Mode
Relation between Writing to TDR and TDRE Flag
Restrictions on Using DTC or DMAC
SCK
TDRE
Serial data
Note: When external clock is supplied, t must be more than four clock cycles.
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7

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