OM11077 NXP Semiconductors, OM11077 Datasheet - Page 92

• Manufacturer Part Number: OM11077
• Description: MODULE DIMM LPC2478 ARM7
• Manufacturer: NXP Semiconductors

Specifications of OM11077

• Accessory Type: Module Card
• For Use With/related Products: ARM-57TS-LPC2478
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-4742

NXP Semiconductors
UM10237_4
User manual
10.21 Static Memory Configuration registers (EMCStaticConfig0-3 -
Table 88.
0xFFE0 8200, 220, 240, 260)
The EMCStaticConfig0-3 registers configure the static memory configuration. It is
recommended that these registers are modified during system initialization, or when there
are no current or outstanding transactions. This can be ensured by waiting until the EMC
is idle, and then entering low-power, or disabled mode. These registers are accessed with
one wait state.
Table 5–89
synchronous burst mode memory devices are not supported.
Table 89.
Bit
9:8
31:10 -
Bit
1:0
2
3
5:4
6
Symbol
Memory width
(MW)
-
Page mode
(PM)
-
Chip select
polarity (PC)
Symbol
CAS latency
(CAS)
Dynamic Memory RAS & CAS Delay registers (EMCDynamicRasCas0-3 - address
0xFFE0 8104, 0xFFE0 8124, 0xFFE0 8144, 0xFFE0 8164) bit description
Static Memory Configuration registers (EMCStaticConfig0-3 - address
0xFFE0 8200, 0xFFE0 8220, 0xFFE0 8240, 0xFFE0 8260) bit description
shows the bit assignments for the EMCStaticConfig0-3 registers. Note that
Rev. 04 — 26 August 2009
Value Description
00
01
10
11
-
0
1
-
0
1
Value Description
00
01
10
11
-
Chapter 5: LPC24XX External Memory Controller (EMC)
8 bit (POR reset value).
16 bit.
32 bit.
Reserved.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
In page mode the EMC can burst up to four external
accesses. Therefore devices with asynchronous page
mode burst four or higher devices are supported.
Asynchronous page mode burst two devices are not
supported and must be accessed normally.
Disabled (POR reset value).
Async page mode enabled (page length four).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
The value of the chip select polarity on power-on reset is
0.
Active LOW chip select.
Active HIGH chip select.
Reserved.
One CCLK cycle.
Two CCLK cycles.
Three CCLK cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
UM10237
© NXP B.V. 2009. All rights reserved.
92 of 792
Reset
Value
11
NA
Reset
Value
0
NA
0
NA
0